Storage device non-fatal error debug system
US12248363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Apr 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0787
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device non-fatal error debug system includes a storage device including a storage device chassis, storage device subsystems housed in the storage device chassis, and a non-fatal error debug subsystem provided in the storage device chassis and coupled to each of the storage device subsystems. The non-fatal error debug subsystem provides a counter system for each of a plurality of data path stages performed by the storage device subsystems to provide data path(s) in the storage device, and monitors each counter system during the execution of commands by the storage device subsystems via the performance of the data path stages. When the non-fatal error debug subsystem determines that a counter system provided for a data path stage performed by a storage device subsystem to provide a data path in the storage device indicates a non-fatal error, it collects debug information associated with that data path stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.