Management of IOMMU TLB entries for compute units of a SIMD processing device
US12248406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2022 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Mar 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application discloses a computing system and an associated method. The computing system includes a memory, a master computing device and a slave computing device. The master computing device includes a memory controller and an input-output memory management unit (IOMMU). When the slave computing device accesses a first virtual address, and a first translation lookaside buffer (TLB) of the slave computing device does not store the first virtual address, the first TLB sends a translation request to the IOMMU. The IOMMU traverses page tables of the memory controller to obtain a first physical address corresponding to the first virtual address, selects and clears a first virtual address entry from a second TLB of the computing system according to a recent use time and a dependent workload of each virtual address entry to store the first virtual address and the first physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.