Optimization processing unit utilizing digital oscillators
US12248532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2021 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Jan 10, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system including digital oscillators and at least one programmable interconnect is described. The programmable interconnect(s) provide weights for and selectably couples at least a portion of the digital oscillators. The digital oscillators and the programmable interconnect(s) form an optimization processing unit (OPU). A system for performing reversible logic is also described. The system includes digital oscillators coupled to perform a logic operation and an error correction unit coupled to the digital oscillators. The error correction unit is configured to sample states of the digital oscillators, detect error(s) in the states, and tune connection coefficient(s) between the oscillators in response to detecting the error(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.