Adder circuit using lookup tables
US12248764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2024 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Feb 27, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.