Distributed shared memory

US12248788B2 · kind B2 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Prakash BANGALORE PRABHAKAR · San Jose, US
• Gentaro Hirota · Sunnyvale, US
• Ronny Meir Krashinsky · San Francisco, US
• Ze Long · San Jose, US
• Brian Pharris · Cary, US
• Rajballav DASH · San Jose, US
• Jeff Tuckey · Saratoga, US
• Jerome F. Duluk, Jr. · Palo Alto, US
• Lacky V. Shah · Los Altos, US
• Luke Durant · San Jose, US
• Jack Choquette · Palo Alto, US
• Eric S. Werness · San Jose, US
• Naman GOVIL · Sunnyvale, US
• Manan Patel · San Jose, US
• Shayani DEB · Seattle, US
• Sandeep Navada · San Jose, US
• John H. Edmondson · Arlington, US
• Greg Palmer · Cedar Park, US
• Wish Gandhi · Santa Clara, US
• Ravi Manyam · Santa Clara, US
• Apoorv Parle · San Jose, US
• Olivier Giroux · Santa Clara, US
• Shirish Gadre · Fremont, US
• Steve HEINRICH · Madison, US

Key dates

• Filing date: Mar 10, 2022
• Grant date: Mar 11, 2025
• Expiry date: Mar 10, 2042

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T1/60
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.