Single bitline SRAM pixel and method for driving the same
US12249299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2022 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Apr 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.