Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit
US12249385B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Oct 12, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.