Semiconductor devices having parasitic channel structures
US12249623B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 8, 2021 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Mar 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The semiconductor device also includes a gate structure that includes first and second portions. The first portion is formed between each nanostructure of nanostructures. The second portion is formed under the bottom-most nanostructure of the plurality of nanostructures and extends under a top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.