Error correction systems and methods
US12250005B2 · kind B2 · utility
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1References
20Claims
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Assignee
Inventor
Key dates
| Filing date | Jun 16, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Jun 16, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6561
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure include techniques for error correction. Multiple successive odd syndromes are generated from input data comprising parity bits. Coefficients are generated and applied to a finite element field to detect multiple bit errors. Error correction circuitry corrects detected error bits. A single bit error detector may detect single bit errors. The error correction circuit may select between a single bit error vector and a multibit error vector based on one of the coefficients. The circuitry may be implemented in combinational logic to perform detection and correction in a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.