Patent · US Active

Network-on-chip topology generation

US12250145B2 · kind B2 · utility

0Cited by

6References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Nitin Agarwal · Bengaluru, IN
Anup Gangwar · Bengaluru, IN
Honnahuggi Harinath Venkata Naga Ambica Prasad · Bengaluru, IN
Ravishankar Sreedharan · Bengaluru, IN
Narayana Sri Harsha Gade · Bengaluru, IN

Key dates

Filing date	Mar 16, 2022
Grant date	Mar 11, 2025
Priority date	—
Expiry date	Sep 9, 2043

Classification

Technology area (CPC H)Electricity
CPC primaryH04L45/42
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A computer-based method and system for synthesizing a Network-on-Chip (NoC) is provided. One method includes determining physical data, device data, bridge data, traffic data and domain data based on an input specification for the NoC; assigning a domain to each bridge port; partitioning each traffic flow into one of a plurality of bins based on the bridge port domain assignments and the domain crossing constraints; creating a virtual node at each bridge port endpoint; generating a candidate topology for each bin based on the physical data, the device data, the bridge data, the traffic data, the domain data and the virtual nodes, each candidate topology including bridge ports, a tree of routers, routes and connections; and generating a final topology by merging the candidate topologies.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.