Image sensor with stacked CCD and CMOS architecture
US12250481B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Mar 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/811
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Image sensor systems are disclosed that include charge coupled device (CCD) pixels integrated with CMOS readout circuitry via separately bonded substrates. According to some embodiments, columns of image sensing pixels on a first substrate are arranged with overlapping gate structures to facilitate charge transfer between the pixels. At least one pixel is coupled to a first conductive pad that contacts (or is melded with) a second conductive pad from a second substrate bonded to the first substrate. The second substrate includes a readout circuit using one or more CMOS devices coupled to the second conductive pad to receive the accumulated charge from a given column of pixels. The resulting photodetector signal from the accumulated charge can be, for instance, amplified via a source follower component and ultimately read out to a column amplifier, and subjected to further processing and/or use in a given downstream system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.