Sensor interposer employing castellated through-vias
US12250768B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Oct 17, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10378
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.