SRAM cell layout including arrangement of multiple active regions and multiple gate regions

US12250804B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Shafquat Jahan Ahmed · Greater Noida, IN
• Dhori Kedar Janardan · Mahesana, IN

Key dates

• Filing date: Aug 23, 2023
• Grant date: Mar 11, 2025
• Expiry date: Aug 23, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/18

Abstract

A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.