One-time programmable memory cell and memory thereof
US12250809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2023 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Nov 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an anti-fuse type one-time programmable memory cell. The memory cell includes a selection transistor and a gate capacitor, which are connected in series and located in a substrate, the substrate including an active region and an isolation region; in which the gate capacitor includes a gate, a gate oxide layer between the gate and the substrate, and an ion-doped region beneath the gate oxide layer, the ion-doped region being located in the active region in the substrate and overlapping with a part of a lower surface of the gate oxide layer; in which a part of the lower surface of the gate oxide layer that does not overlap with the ion-doped region completely overlaps with the isolation region in the substrate, and the ion-doped region and the isolation region are seamlessly adjacent to each other in the substrate beneath the gate oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.