Pixel structure, array substrate and fabrication method thereof
US12250837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2022 |
| Grant date | Mar 11, 2025 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/134345
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A pixel structure includes: a gate electrode disposed on a base substrate; a gate insulation layer covering the gate electrode; a source electrode, an active region, a drain electrode, a first doped region and a secondary electrode metal layer disposed on an upper surface of the gate insulation layer sequentially; two second doped regions at two ends of an upper surface of the active region; and a passivation layer covering source electrode, a portion of the active region exposed to the second doped regions, the second doped regions, the drain electrode, the first doped region and the secondary electrode metal layer. The passivation layer is provided with a primary pixel electrode and a secondary pixel electrode disposed thereon, the primary pixel electrode is connected to the drain electrode, and the secondary pixel electrode is connected to the secondary electrode metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.