Software-defined coherent caching of pooled memory
US12253948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2020 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Apr 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/742
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be evicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.