PCIe deterministic link training using OOB communications and enumeration optimization during different power-up states
US12253966B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2021 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Jul 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Peripheral Component Interface Express (PCIe) card includes a circuit board, a device mounted on the circuit board, and a PCIe processor mounted on the circuit board. The PCIe processor is communicatively coupled to the device and a host processor of a host system. The PCIe processor is configured to detect a power signal on an auxiliary (AUX) power rail of the PCIe card. A periodic detection of a state of the device is performed based on detecting the power signal on the AUX power rail. A signal indicative of the state of the device is encoded for transmission to the host processor of the host system. PCIe link training is performed via a PCIe interface with the host system. The PCIe link training is initiated based on the signal indicative of the state of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.