Method of resetting integrated circuit with synchronous reset signal, and integrated circuit
US12254321B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 19, 2021 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Aug 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of resetting an integrated circuit, includes: generating, in response to a reset signal intended for a first data unit, a synchronous reset signal based on the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period; and generating, in response to a first data signal output by the first data unit, a second data signal based on the synchronous reset signal and the first data signal, and outputting the second data signal to a second data unit. An integrated circuit is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.