Use of configurable phase range to detect DDR read and write bursts
US12254935B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Apr 11, 2023 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Apr 11, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method (and corresponding system, computer program and storage device) for testing a device under test, DUT, comprising: generating or receiving, by a component of the DUT, a bus signal, wherein the bus signal comprises a first data signal having a plurality of first phase angles or a second data signal having a plurality of second phase angles; averaging the phase angles for a predetermined bus signal length; comparing the averaged phase angle with a preset phase range; and identifying the first data signal or the second data signal in the bus signal based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.