Control method, semiconductor memory, and electronic device
US12254942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2023 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Jun 9, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control method includes: decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, the impedance of a Data Mask (DM) pin to be a first value; or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP; wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.