Semiconductor devices including a support pattern on a lower electrode structure
US12255065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2023 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Dec 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.