Method of back end of line via to metal line margin improvement
US12255134B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 8, 2022 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Jul 19, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes forming a plurality of lower level conductive lines in a first dielectric layer. The plurality of lower level conductive lines includes a first lower level conductive line. The method further includes recessing portions of the first lower level conductive line below a top surface of the first dielectric layer to form a recess, forming a dielectric cap in the recess, depositing a second dielectric layer over the first dielectric layer. Forming a via opening exposes a portion of the second lower level conductive line. The method further includes forming an upper level conductive line and a via in the trench and in the via opening, respectively. The via couples the upper level conductive line to the second lower level conductive line, and the upper level conductive line overlaps with the dielectric cap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.