Semiconductor structure having two N-type devices and two P-type devices and manufacturing method thereof
US12256568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2022 |
| Grant date | Mar 18, 2025 |
| Priority date | — |
| Expiry date | Jul 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor structure includes the following operations. A substrate is provided, which includes a first N region, a first P region, a second N region and a second P region adjacently arranged in sequence. A gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are formed on the substrate in sequence. A mask layer is formed on the second barrier layer of the first P region and the second P region. The second barrier layer of the first N region and the second N region is removed by a first etching process with the mask layer as a mask. The first work function layer and the first barrier layer of the first N region and the second N region are removed by a second etching process. A semiconductor structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.