Architecture for managing asynchronous resets in a system-on-a-chip
US12259764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jun 28, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/22
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.