Processor-based system for allocating cache lines to a higher-level cache memory
US12259820B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 2024 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Apr 2, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-based system for allocating a higher-level cache line in a higher-level cache memory in response to an eviction request of a lower-level cache line is disclosed. The processor-based system determines whether the cache line is opportunistic, sets an opportunistic indicator to indicate that the lower-level cache line is opportunistic, and communicates the lower-level cache line and the opportunistic indicator. The processor-based system determines, based on the opportunistic indicator of the lower-level cache line, whether a higher-level cache line of a plurality of higher-level cache lines in the higher-level cache memory has less or equal importance than the lower-level cache line. In response, the processor-based system replaces the higher-level cache line in the higher-level cache memory with the lower-level cache line and associates the opportunistic indicator with the lower-level cache line in the higher-level cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.