Deterministic near-compute memory for deterministic processor and enhanced data movement between memory units and processing units
US12260118B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Mar 1, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A deterministic apparatus comprising a deterministic near-compute memory communicatively coupled with and proximate to a deterministic processor. The deterministic near-compute memory comprises a plurality of data banks having a global memory address space, a control bus, a data input bus and a data output bus for each data bank. The deterministic processor is configured to initiate, via the control bus, retrieval of a set of data from the plurality of data banks. The retrieved set of data comprises at least one row of a selected one of the data banks passed via the data output bus onto a plurality of stream registers of the deterministic processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.