Layout-based data transfer between synchronized, interconnected processing elements for implementing machine learning networks
US12260253B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 23, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jul 8, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A machine learning accelerator (MLA) implements a machine learning network (MLN) by using data transfer instructions that coordinate concurrent data transfers between processing elements. A compiler receives a description of a machine learning network and generates the computer program that implements the MLN. The computer program contains instructions that will be run on PEs of the MLA. The PEs are connected by data transfer paths that are known to the compiler. The computations performed by the PEs may require data stored at other PEs. The compiler coordinates the data transfers to avoid conflicts and increase parallelism.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.