Decoder driver circuit and memory chip
US12260899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jul 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to a decoder driver circuit and a memory chip. The decoder driver circuit includes: a plurality of sub drive units configured to generate a main word line drive signal according to a power supply voltage signal, a first decoding input signal and an intermediate decoding output signal; and a plurality of decoding control circuits connected to the plurality of sub drive units, where the plurality of decoding control circuits are configured to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal. When the intermediate decoding output signal is in a first state, the main word line drive signal is in a non-drive state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.