Complementary storage unit and method of preparing the same, and complementary memory
US12260902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2020 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Feb 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.