Memory circuit structure and method of operating memory circuit structure
US12260911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2021 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Oct 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory circuit structure includes: a storage array, wherein the storage array includes at least two storage units; a decoder connected with a bit line and a word line of the storage array respectively; a programming circuit configured to generate a voltage pulse or a constant current pulse; a polarity switching circuit connected with the programming circuit, and configured to implement a switching between a voltage programming and a current programming of the programming circuit under a set operation and a reset operation; a detection circuit connected with the storage array, and configured to detect a detection signal of a current or a voltage corresponding to the specific storage unit in the storage array and feed back the detection signal to a control unit, wherein the detection signal output by the detection circuit is configured to enable the polarity switching circuit to switch; and the control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.