Data receiving circuit, data receiving system, and memory device
US12260933B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jul 19, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a data receiving circuit, a data receiving system, and a memory device. The data receiving circuit includes: a receiving module, configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and a decision feedback equalization module, connected to a feedback node of the receiving module, and configured to perform a decision feedback equalization on the receiving module on the basis of a feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained on the basis of data received previously, and an adjustment capability of the decision feedback equalization module to the first output signal and the second output signal is adjustable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.