Semiconductor structures and manufacturing methods thereof
US12261046B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2024 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Apr 4, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.