Signal lines in memory devices and methods for forming the same
US12261112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jun 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a bit line group having a first bit line and a second bit line. The bit line group includes a first segment, a second segment, and a twist segment conductively connected to the first segment and the second segment. The first segment includes a first portion of the first bit line and a first portion of the second bit line. The second segment includes a second portion of the first bit line and a second portion of the second bit line. The twist segment includes a third portion of the first bit line and a third portion of the second bit line. The first and second portions of the first bit line and the second bit line each extends in a first lateral direction. The third portion of the first bit line is conductively connected to the first and second portions of the first bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.