Compact frequency-locked loop architecture for digital clocking
US12261612B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Sep 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/143
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.