Receivers and method with fast sampling phase and frequency acquisition
US12261928B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2023 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Jul 29, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Fast sampling phase and frequency acquisition suitable for incorporation into various high bandwidth receivers and receiving methods. One illustrative integrated circuit receiver or “deserializer” design has: a clock circuit that provides a sample clock; an analog to digital converter that samples a receive signal in accordance with the sample clock to provide receive signal samples; and a clock recovery circuit. The clock recovery circuit includes: a phase and frequency acquisition module to determine and correct an initial frequency offset and an initial phase offset of the sample clock; and a feedback circuit to minimize timing error of the sample clock after the initial frequency offset and initial phase offset have been corrected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.