Semiconductor structure preparation method, semiconductor structure and semiconductor memory
US12262525B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Mar 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory. The method includes the following operations. An initial semiconductor structure is formed on a substrate. The initial semiconductor structure is etched to form an array area structure and a peripheral area structure including a peripheral area gate structure. An isolation wall surrounding the peripheral area gate structure is formed on the substrate where the peripheral area structure locates. A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure. The second dielectric layer, the first dielectric layer and the isolation wall are etched to form the semiconductor structure with a flat surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.