Semiconductor structure and manufacturing method thereof
US12262550B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2024 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Dec 12, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure is provided. A substrate including a first silicon carbide layer and a second silicon carbide layer under the first silicon carbide layer is formed. The substrate includes a unit region and a termination region surrounding the unit region. A first guard ring structure is formed in the termination region and the first silicon carbide layer, adjoining a top surface of the first silicon carbide layer. A second guard ring structure is formed in the termination region and the second silicon carbide layer. Second guard ring well regions of the second guard ring structure correspond one-on-one to first guard ring well regions of the first guard ring structure. Each of the second guard ring well regions overlaps with a corresponding one of the first guard ring well regions in a vertical direction perpendicular to the top surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.