Semiconductor device and method of manufacturing the same
US12262558B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2022 |
| Grant date | Mar 25, 2025 |
| Priority date | — |
| Expiry date | Aug 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.