Memory controller for controlling allocation ratio of buffer memory, memory system including the same, and method of operating memory controller
US12265727B2 · kind B2 · utility
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9References
18Claims
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Key dates
| Filing date | Nov 9, 2022 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Jan 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory controller configured to control a memory device and sub-buffer memory arranged outside the memory controller. The memory controller includes a processor configured to control a memory operation for the memory device, main buffer memory that is different from the sub-buffer memory and arranged in the memory controller, and a buffer allocation circuit configured to control an allocation ratio between the sub-buffer memory and the main buffer memory. The processor sets an operation mode of the buffer allocation circuit as an operation in which the allocation ratio is fixed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.