Quality of service techniques in distributed graphics processor
US12265844B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2021 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Aug 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed techniques relate to circuitry configured to aggregate and report usage information in a distributed processor (e.g., a GPU). In some embodiments, graphics processor circuitry that includes at least first and second portions that are respectively configured to execute sets of graphics work. First utilization circuitry may track execution time for sets of graphics work on the first portion of the graphics processor circuitry and second utilization circuitry may track execution time for sets of graphics work on the second portion of the graphics processor circuitry. Command queue circuitry may store multiple different command queues. Control circuitry may access the first and second utilization circuitry and aggregate utilization data on a per-command-queue basis, where for a given command queue, the aggregated utilization data indicates respective utilization of the first and second portions of the graphics processor circuitry. The control circuitry may provide the aggregated per-command-queue utilization data in software-accessible registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.