Memory device and test method of memory device
US12266414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2022 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Sep 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a memory device including a cell array, a peripheral circuit configured to control a memory operation of the plurality of memory cells, a test logic circuit configured to operate in a test mode and configured to perform a test operation on the plurality of memory cells, a first regulator configured to regulate a first power supply voltage received through a first pad and provide the first power supply voltage to at least one of the cell array and the peripheral circuit, and a power manager between the first pad and an input terminal of the first regulator, and between the first pad and the test logic circuit and configured to provide a test power supply voltage to the test logic circuit. In the test mode, while a first target voltage level of the first regulator fluctuates, a second target voltage level of the power manager is maintained constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.