Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same
US12266575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2024 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Feb 5, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.