Array substrate, manufacturing method thereof, and display panel
US12266662B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | May 19, 2021 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Dec 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/443
Abstract
An array substrate, a manufacturing method thereof, and a display panel are provided. By disposing first electrodes and second electrodes on top and bottom sides of an active layer, respectively, and disposing a part of each gate electrode among sub-active patterns, the array substrate is formed with vertical-structured thin film transistors. Therefore, a channel resistance can be reduced, and a channel width of the thin film transistors can be reduced, thereby reducing an area of the thin film transistors, reducing impedance of the thin film transistors, and reducing power consumption of the display panel.
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