Single-event effect tolerant register
US12267069B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2024 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Oct 22, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A resilient majority driver accepts triple-redundant input signals and provides a robust output signal unaffected by static errors on one of the input signals or by single-event transients caused by radiation within the driver. Data, clock, and asynchronous input signals to DICE (Dual Interlocked storage CEll) flip-flops in a register are driven by resilient majority drivers to construct an input-protected DICE register. Static errors are corrected using triple-redundant inputs and majority voting, while single-event strikes are largely corrected by the DICE architecture within each flip-flop and by the resilient majority drivers. Remaining errors in the input-protected DICE registers, such as those caused by single-event transients occurring during clock transitions, are corrected by error-correction encoders and decoders, whose output transients are suppressed by glitch filters. A resulting single-event effect tolerant register is more compact than a triple-redundant DICE register and requires no continuous external clock to correct errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.