Signal receiving apparatus, clock and data recovery circuit and clock and data recovery method thereof
US12267076B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2023 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Nov 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2275
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a clock and data recovery circuit. A sampling circuit performs burst mode over-sampling on an input analog data signal according to a sampling timing in a burst mode to generate over-sampling results. A selection circuit determines neighboring two of the over-sampling results having opposite logic states in the burst mode to select data edge sampling results and data center sampling results interlaced with each other and having the same time period with input analog data signal from the over-sampling results accordingly to be output sampling results. A phase detection circuit performs phase detection according to the output sampling result to generate a phase locking direction. A phase adjusting circuit adjusts the sampling timing of the sampling circuit according to the phase locking direction to track the input analog data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.