Pixel architecture with multiple pixel binning
US12267605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2022 |
| Grant date | Apr 1, 2025 |
| Priority date | — |
| Expiry date | Apr 13, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/771
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Structures are disclosed for a binned set of two or more pixels of a pixel array that share a same readout circuit. The binned pixel design provides space-saving benefits on the chip and also improves the overall image quality. According to some embodiments, each of the binned pixels includes a photodetector and its own transfer gate. The readout circuit is coupled to the transfer gates of each of the binned pixels and includes its own second transfer gate that separates the pixels from a gain mode select block. The gain mode select block may include capacitors of different sizes and one or more switches to control which capacitors are to receive the charge from any one of the binned pixels. The readout circuit may also include a potential barrier (such as a diode), which allows for pumping charge onto the one or more capacitors of the gain mode select block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.