Dielectric protection layer configured to increase performance of mems device
US12269735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2022 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Jan 16, 2043 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/053
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Various embodiments of the present disclosure are directed towards an integrated chip including an interconnect structure overlying a semiconductor substrate. An upper dielectric structure overlies the interconnect structure. A microelectromechanical system (MEMS) substrate overlies the upper dielectric structure. A cavity is defined between the MEMS substrate and the upper dielectric structure. The MEMS substrate comprises a movable membrane over the cavity. A cavity electrode is disposed in the upper dielectric structure and underlies the cavity. A plurality of stopper structures is disposed in the cavity between the movable membrane and the cavity electrode. A dielectric protection layer is disposed along a top surface of the cavity electrode. The dielectric protection layer has a greater dielectric constant than the upper dielectric structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.