Device and method for operating memory in electronic device
US12271288B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Oct 4, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory operation device and method for operating a memory in an electronic device. The electronic device may determine whether a memory leak occurs in one or more low-order stack trace items with a count value of n among collected stack trace items, n being a positive integer, and, based on a low-order stack trace item among the collected stack trace items being determined as causing a memory leak, proceeding to a next order of the collected stack trace items to thereby determine whether a memory leak occurs in one or more high-order stack trace items with a count value of m which is a positive integer higher than n). When m is a maximum count value among the collected stack trace items, memory debugging may be performed using a high-order stack trace item, among the one or more high-order stack trace items, causing the memory leak.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.