Controller for locking of selected cache regions
US12271308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2023 |
| Grant date | Apr 8, 2025 |
| Priority date | — |
| Expiry date | Dec 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.