Patent · US Active

Method and device for authenticating an FPGA configuration

US12271512B2 · kind B2 · utility

0Cited by

6References

15Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Fabrizio De Santis · Munich, DE
Markus Dichtl · Birkenfeld, DE

Key dates

Filing date	Nov 19, 2019
Grant date	Apr 8, 2025
Priority date	—
Expiry date	Mar 30, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/26
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

The disclosure relates to a method and a device for authenticating an FPGA configuration. The method includes at least partly reading the configuration of a FPGA by the FPGA itself and calculating a first checksum using the read configuration. The method further includes providing an authentication response which confirms that the FPGA configuration is authentic when the first checksum matches a specified checksum, wherein the reading, calculating, and providing are carried out in an obfuscated manner. The authentication response confirming that the FPGA configuration is authentic is not provided or is only provided with a very low degree of probability when the first checksum and the specified checksum do not match. In this regard, an FPGA may check its own configuration.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.